SRC and DARPA sponsored ASCENT center (ascent.nd.edu) continues its strong presence at the 2021 IEEE International Electron Devices Meeting (IEDM) with a new record of 12 contributed papers and 2 invited papers. IEDM is is the world's preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. The papers show progress in a variety of domains such as gallium nitride based transistors for efficient power delivery, atomically thin channel transistors, ultra-thin gate stack transistors, back-end-of-the-line (BEOL) compatible thin film transistors, monolithic 3D integration of ternary content addressable memory stacks, capacitorless cryogenic DRAM and various genres of in-memory compute fabrics.

Highlights:

5-4 GaN/AlGaN superlattice based E-mode p-channel MES-FinFET with regrown contacts and >50mA/mm on-current, A. Raj, A. Krishna, N. Hatui, B. Romanczyk, C. Wurm, M. Guidry, R. Hamwey, N.Pakala, S. Keller, and U. K. Mishra, Department of Electrical and Computer Engineering, University of California Santa Barbara • In this work, we report on GaN/AlGaN superlattice based MES-FinFET devices with MOCVD regrown p+ contacts around the fins. 75 nm wide FinFETs showed a normally-off operation with an on-current of 65 mA/mm, the highest ever reported for any GaN based E-mode pFETs. Simultaneously, a large Ion/Ioff >107 was also achieved.

6-1 Trap Capture and Emission Dynamics in Ferroelectric Field-Effect Transistors and their Impact on Device Operation and Reliability, N. Tasneem, Z. Wang, Z. Zhao*, N. Upadhyay**, S. Lombardo, H. Chen, J. Hur, D. Triyoso***, S. Consiglio***, K. Tapily***, R, Clark***, G. Leusink***, S. Kurinec*, S. Datta**, S. Yu, Kai Ni*, M. Passlack#, W. Chern, A. Khan, Georgia Tech, *Rochester Institute of Technology **University of Notre Dame School of MSE, Georgia Tech, ***TEL Technology Center, America, LLC, # Taiwan Semiconductor Manufacturing Company Company • We track carrier capture and emission dynamics during write operations in n-type ferroelectric-field-effect transistors by directly and separately measuring the trap related hole and electron currents through the body terminal and shorted source-drain, respectively. The universality of the suggested mechanisms is confirmed in different FEFETs fabricated in different facilities.

7-3 Sub-200 Ω·μm Alloyed Contacts to Synthetic Monolayer MoS2, A. Kumar, K. Schauble, K. M. Neilson, A. Tang, P. Ramesh, H.-S. Philip Wong, E. Pop, K. Saraswat. Stanford University • We demonstrate ultra-low contact resistance to monolayer MoS2 of 190 Ω⋅μm using In-Au alloy and 270 Ω⋅μm using Sn-Au alloy contacts, which are among the best reported to date. We perform a statistical study of 720 transistors, revealing the ‘best’ and ‘average’ alloyed contacts, for the first time.

13-6 Demonstration of Low EOT Gate Stack and Record Transconductance on Lg=90 nm nFETs Using 1.8 nm Ferroic HfO2-ZrO2 Superlattice, W. Li, L. C. Wang*, S. S. Cheema*, N. Shanker, J. H. Park, Y. H. Liao, S. L. Hsu, C. H. Hsu, S. Volkman, U. Sikder, A. J. Tan, J. H. Bae, C. Hu, S. Salahuddin University of California, *University of California • Enhanced gate capacitance and associated low EOT is demonstrated in a 1.8-nm ferroic HfO 2ZrO2 superlattice gate stack on n-MOSFETs without any IL scavenging, resulting in record-high intrinsic transconductance of 1.5 mS/μm and a 14% I on increase in 90-nm transistors. The capacitance enhancements show no dispersion up to 25 GHz.

17-1 Lifelong Learning with Monolithic 3D Ferroelectric Ternary Content-Addressable Memory, S. Dutta, A. Khanna, H. Ye, M.M. Sharifi, A. Kazemi, M. San Jose, K.A. Aabrar, J.G. Mir, M. Niemer, X.S. Hu and, S. Datta, University of Notre Dame • We present array-level demonstration of few-shot learning using a first time fabricated monolithic 3D TCAM using BEOL FeFETs. We experimentally demonstrate write voltage of 1.6V,20ns write latency for BEOL FeFETs , in situ computation of Hamming distance between a 20-bit search vector and stored vectors, and high write endurance> 10 10 cycles.

17-4 High-Peformance BEOL-Compatible Atomic-Layer-Deposited In2O3 Fe-FETs Enabled by Channel Length Scaling down to 7 nm: Achieving Performance Enhancement with Large Memory Window of 2.2 V, Long Retention > 10 years and High Endurance > 10^8 Cycles, Z. Lin, M. Si, Y.-C.Luo*, X. Lyu, A. Charnas, Z. Chen, Z. Yu*, W. Tsai**, P. C. McIntyre**, R. Kanjolia***, M.Moinpour***, S. Yu*, P. D. Ye*, Purdue University, *Georgia Institute of Technology, **StanfordUniversity, *** EMD Electronics • In this work, we report ultra-scaled ALD In2O3Fe-FETs with channel length down to 7 nm as back-end-of-line compatible non-volatile memory devices, achieving memory performance enhancement with a memory window of 2.2 V, retention over 10 years, and endurance over 10⁸ cycles, demonstrating the key advantage of scaling in Fe-FETs.

19-3 Standby Bias Improvement of Read After Write Delay in Ferroelectric Field Effect Transistors, Zheng Wang, Nujhat Tasneem, Jae Hur, Hang Chen, Shimeng, Yu, Winston Chern, Asif Khan, Georgia Institute of Technology • Read after write is a significant challenge in FEFETs because the speed limitation of neutralizing interfacial traps. We investigated two approaches to by passing the fundamental limitation. We reduced the delay to 400 ns by applying a standby bias of ±1.5V, making the device 105 times faster.

19-4 FeFETs for Near-Memory and In-Memory Compute, (Invited), S. Salahuddin, A. Tan, S.Cheema, N. Shanker, M. Hoffmann, J.-H Bae, University of California Berkeley • Ferroelectric Field Effect Transistors (FeFETs) have seen resurgence in the recent years with the advent of doped HfO2 as a ferroelectric material [1]. Here we will discuss the potential and challenges for FeFETs as a memory solution for near-memory and in-memory computing.

19-6 BEOL Compatible Superlattice FerroFET-based High Precision Analog Weight Cell with superior Linearity and Symmetry, K.A. Aabrar, J. Gomez, S.G. Kirtania, M.S. Jose, Y. Luo*, P.G.Ravikumar**, P.V. Ravindran*, H. Ye, S. Banerjee, S. Dutta, A.I. Khan*, S. Yu*, S. Datta. University of Notre Dame, *Georgia Institute of Technology, **Indian Institute of Technology Palakkad • We engineer the ferroelectric domain in a superlattice (SL) FE/DE stack, to demonstrate high precision FEFET analog weight cells with linearity and symmetry during potentiation and depression. We demonstrate switching speed of 100 ns. We integrate the SL with a BEOL compatible IWO transistor to demonstrate 128 conductance states.

21-4 Experimental Demonstration of Non-volatile Capacitive Crossbar Array for In-memory Computing, Y-C Luo, J. Hur, T-H Wang, A. Lu, S. Li, A. Islam Khan, S. Yu. Georgia Institute of Technology • Non-volatile ferroelectric Hf0.5Zr0.5O2 capacitive-crossbar array has been experimentally demonstrated with highly-linear vector-matrix multiplication. This design consumes only dynamic power, has no DC sneak paths and negligible IR drop along wires, and is compatible with 3D-stacking architecture. Array-level SPICE simulation shows 20~200x lower energy consumption than that of a resistive counterpart.

25-2 In-Memory Computing with Associative Memories — A Cross-Layer Perspective, (Invited), X.S.Hu, M. Niemier, A. Kazemi, A.F. Laguna, K. Ni*, R. Rajaei, X. Yin**, University of Notre Dame,*Rochester Institute of Technology, **Zhejiang University • Associative memory (AM), which efficiently “associates” an input query with appropriate data words/locations in the memory, is a powerful in-memory-computing core. This paper showcases representative AM designs based on non-volatile memory technologies. End-to-end evaluations for machine learning applications are discussed to demonstrate the benefits contributed by each design layer.

25-3 Monolithic 3D Compute-in-Memory Accelerator with BEOL Transistor based Reconfigurable Interconnect, (Invited), Y. Luo, S. Dutta*, A. Kaul, S-K Lim, M. Bakir, S. Datta*, S. Yu, GeorgiaInstitute of Technology, *University of Notre Dame • CIM-based inference engine's area scaling is limited by availability of logic voltage compatible NVM at leading-edge node. This work performs system-technology co-design (STCO) of a monolithic 3D (M3D) CIM accelerator using the back-end-of-line (BEOL) compatible oxide channel (IWO) MOSFET for write circuit and the IWO-based FeFET for reconfigurable interconnect.

37-6 Computational Associative Memory Based on Monolithically Integrated Metal-Oxide Thin Film Transistors for Update-Frequent Search Applications, Z. Zhao, J. Gomez*, H. Ye*, M. Imani**, X.Yin***, S. Deng, B. Melanson, J. Zhang, X. Gong^^, A. Abusleme^^^, S. Datta*, and K. Ni, Rochester Institute of Technology, *University of Notre Dame, **University of California, ^Zhejiang University,^^National University of Singapore, ^^^Pontificia Universidad Católica de Chile • Monolithic 3D TCAM designs based on TFTs that can achieve high density and excellent write performance for update-frequent search applications are demonstrated. Logic-compatible write voltage (,1.5V), ,20ns write latency, >1010 endurance are achieved. Up to 14x/35x improvement in speed/energy over GPU in accelerating the K-Means clustering algorithm.

40-1 Pseudo-Static 1T Capacitorless DRAM using 22nm FDSOI for Cryogenic Cache Memory, W. Chakraborty, R. Saligram*, A. Gupta, M. San Jose, K. A. Aabrar, S. Dutta, A. Khanna, A. Raychowdhury*and S. Datta, University of Notre Dame, *Georgia Institute of Technology • We experimentally demonstrate, for the first time, pseudo-static random access memory operation of a 1T Capacitorless Floating Body DRAM using 22nm FDSOI transistor, down to 4.8K, for cryogenic cache memory. We demonstrate a 1T Cryo-DRAM that exhibit record high sensing current and sense margin, pseudo-static retention characteristics >105sec.